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18 ghz microwave pll synthesizer data sheet ADF41020 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any paten t or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2012 analog devi ces, inc. all rights reserved. technical support www.analog.com features 18 ghz maximum rf input frequency integrated sige prescaler software compatible with the adf410 6 / adf4107 / adf4108 family of plls 2.85 v to 3.15 v pll power supply programmable dual - modulus prescaler 8/9, 16/17, 32/33, 64/65 programmable charge pump currents 3 - wire serial interface analog and digital lock detect hardware and software power - down mode applications microwave point - to - point/m ulti p oint r adios wireless infrastructure vsat r adios t est equipment instrumentation general description the ADF41020 frequency synthesizer can be used to implement local oscillators as high as 18 ghz in the up conversion and down conversion sections of wireless receivers and transmitters. it consists of a low noise , digital phase frequency detector (pfd ), a precision charge pump, a p rogrammable reference divider , and high frequency programmable feedback dividers (a, b , and p) . a co mplete phase - locked loop (pll) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (vco). the synthesizer can be used to drive external microwave vcos via an active loop filter. it s very high bandwid th means a frequenc y doubler stage can be eliminated, simplifying system architecture and reducing cost . the ADF41020 is software - compatible with the existing adf4 106/ adf4107 / adf4108 family of devices from analog devices , inc . the ir pinout s match very closely with the exception of the ADF41020 s single - ended rf input pin, meaning only a minor layout change is required when updating current design s. functional block diagram figure 1. clk data le ref in rf in 24-bit input register av dd dv dd ce gnd gnd r counter r counter latch function latch a, b counter latch p/p+ 1 n = 4(bp + a) a and b m3 m2 m1 mux sd out av dd high-z muxout gnd r set v p cp phase frequency detector lock detect reference charge pump current setting 1 ADF41020 cpi3 cpi2 cpi1 cpi6 cpi5 cpi4 current setting 2 50? 3pf counters divide by 4 10304-001
ADF41020 data sheet rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ................................................................ 4 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 theory of operation ........................................................................ 8 reference input section ............................................................... 8 rf input stage ................................................................................8 prescaler ..........................................................................................8 a counter and b counter ............................................................8 r counter .......................................................................................9 pfd and charge pump .................................................................9 muxout and lock detect .........................................................9 input shift register .......................................................................9 the function latch .................................................................... 13 applications information .............................................................. 15 interfacing ................................................................................... 15 pcb design guidelines ............................................................. 15 outline dimensions ....................................................................... 16 ordering guide .......................................................................... 16 revision history 10/12revision 0: initial version
data sheet ADF41020 rev. 0 | page 3 of 16 specifications d v dd = a v dd = v p = 3 .0 v 5 %, gnd = 0 v, r set = 5.1 k?, dbm referred to 50 ?, t a = t max to t min , unless otherwise noted. table 1 . parameter min typ max unit test conditions/comments rf characteristics see figure 1 for input circuit rf input frequency (rf in ) 4.0 18.0 ghz rf input sensitivity ? 10 +10 dbm maximum allowable prescaler output frequency 1 350 mhz ref in characteristics ref in input frequency 10 400 mhz for f < 10 mhz, ensure slew rate > 50 v/s ref in input sensitivity 0.8 dv dd v p -p biased at dv dd / 2 when input is ac - coupled ref in input capacitance 10 pf ref in input current 100 a phase detector phase detector frequency 2 100 mhz charge pump programmable, see figure 17 i cp sink/source high value 5.0 ma with r set = 5.1 k? low value 625 a absolute accuracy 3 % with r set = 5.1 k? r set 5.1 5.1 5.1 k? see figure 17 i cp three - state leakage 1 2 na t a = 25c sink and source current matching 2 % 0.5 v v cp v p ? 0.5 v i cp vs. v cp 1 % 0.5 v v cp v p ? 0.5 v i cp vs. temperature 2 % v cp = v p /2 logic inputs v ih , input high voltage 1.4 v the spi interface is 1.8 v and 3 v logic compatible v il , input low voltage 0.6 v i inh , i inl , input current 1 a c in , input capacitance 10 pf logic outputs v oh , output high voltage 1.4 v open - drain output chosen, 1 k? pull - up resistor to 1.8 v v oh , output high voltage dv dd ? 0.4 v cmos output chosen i oh , output high current 500 a v ol , output low voltage 0.4 v i ol , output low current 500 a power supplies av dd 2.85 3. 15 v dv dd 2.85 3. 15 v v p 2.85 3. 15 v i dd 3 27 30 ma t a = 25c i p 3 4.5 5 ma t a = 25c power - down mode 1 a t a = 25c
ADF41020 data sheet rev. 0 | page 4 of 16 parameter min typ max unit test conditions/comments noise characteristics normalized phase noise floor 4 ? 221 dbc/hz pll lo op bandwidth = 500 khz normalized 1/f noise 5 ? 118 dbc/hz normalized to 10 khz offset at 1 ghz phase noise performance 6 at vco output 5.7 ghz ? 89 dbc/hz at 1 khz offset and 2.5 mhz pfd frequency with 20 khz l oop bandwidth 12.5 ghz 7 ? 8 2 dbc/hz at 3 khz offset and 2.5 mhz pfd frequency with 20 khz l oop b andwidth 17.64 ghz ? 96 dbc/hz at 100 khz offset and 90 mhz pfd frequency with 700 khz l oop b andwidth spurious signals 5.7 ghz ? 80/ ? 86 dbc at 2.5 mhz/5 mhz and 2.5 mhz pfd frequency 12.5 ghz 7 ? 98/ADF41020eb1z evaluation board and the rohde & schwarz fsup spectrum analyzer. timing characteristi cs a v dd = d v dd = v p = 3.0 v, g n d = 0 v, r set = 5.1 k?, dbm referred to 50 ?, t a = t max to t min , unless otherwise noted. table 2 . parameter limit unit test conditions/comments t 1 10 ns min data to clk setup time t 2 10 ns min data to clk hold time t 3 25 ns min cl k high duration t 4 25 ns min cl k low duration t 5 10 ns min cl k to le setup time t 6 20 ns min le pulse width f igure 2 . timing diagram clk db22 db2 data le t 1 le db23 (msb) t 2 db1 (control bit c2) db0 (lsb) (control bit c1) t 3 t 4 t 6 t 5 10304-002
data sheet ADF41020 rev. 0 | page 5 of 16 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating av dd to gnd ?0.3 v to +3.9 v av dd to dv dd ?0.3 v to +0.3 v v p to gnd ?0.3 v to +3.9 v v p to av dd ?0.3 v to +0.3 v digital i/o voltage, ref in to gnd ?0.3 v to dv dd + 0.3 v analog i/o voltage to gnd ?0.3 v to v p + 0.3 v ref in , rf in to gnd ?0.3 v to av dd + 0.3 v operating temperature range industrial ?40c to +85c storage temperature range ?65c to +125c maximum junction temperature 150c lfcsp ja thermal impedance 1 (paddle soldered) 62.82c/w reflow soldering peak temperature 260c time at peak temperature 40 sec transistor count cmos 6610 bipolar 358 1 two signal planes (that is, on the top and bottom surfaces of the board), two buried planes, and four vias. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device is a high performance rf integrated circuit with an esd rating of <2 kv, and it is esd sensitive. proper precautions should be taken for handling and assembly. esd caution
ADF41020 data sheet rev. 0 | page 6 of 16 pin configuration an d function descripti ons figure 3. pin configuration table 4 . pin function descriptions pin no. mnemonic description 1 , 2, 3, 5, 9, 10 gnd ground pins . 4 rf in input to the rf prescaler. this input is ac - coupled internally . 6, 7 a v dd analog power s upply. this may range from 2.85 v to 3.15 v . d ecoupling capacitors to the ground plane should be placed as close as possible to this pin . pin 6 is the supply for the fixed divide -by - 4 prescaler. 8 ref in reference input. this is a cmos input with a n ominal threshold of dv dd /2 and a dc equivalent input resistance of 100 k? (s ee figure 9 ) . this input can be driven from a ttl or cmos crystal oscillator or it can be ac - coupled. 11 ce chip enable. a logic low on this pin powers down the device and puts the charge pump output into three - state mode. taking the pin high powers up the device, depending on the s tatus of the power - down bit, pd1 . 12 clk serial clock input. this serial clock is used to clock in the serial data to the registers. the data is latched into the 24 - bit shift register on the clk rising edge . this is a high impedance cmos input. 13 data serial data input. the serial data is loaded msb first with the two lsbs being the control bits. this is a high impedance cmos input. 14 le load enable, cmos input. when le goes high, the data stored in the shift registers is loaded into one of the four latches with the latch being selected using the control bits. 15 muxout this multiplexer output allows either the lock detect, the scaled rf, or the scaled reference frequency to be accessed externally. 16, 17 dv dd digital power supply. this may range from 2.85 v to 3.15 v . d ecoupling capacitors to the g round plane should be placed as close as possible to this pin . dv dd must be the same value as av dd . 18 v p charge pump power supply. 19 r set connecting a resistor between this pin and gnd sets the maximum charge pump output current. the nominal voltage potential at the r set pin is 0.66 v. the relationship between i cp and r set is set max cp r i = so, with r set = 5.1 k?, i cp max = 5.0 ma. 20 cp charge pump output. when enabled , this provides i cp to the external loop filter, which in turn drives the external vco. ep exposed pad. the exposed pad must be connected to gnd. 14 13 12 1 3 4 le 15 muxout dat a clk 11 ce gnd gnd 2 gnd rf in 5 gnd 7 av dd 6 av dd 8 ref in 9 gnd 10 gnd 19 r set 20 cp 18 v p 17 dv dd 16 dv dd top view notes 1. the exposed pad must be connected to gnd. ADF41020 10304-003
data sheet ADF41020 rev. 0 | page 7 of 16 typical performance characteristics figure 4. rf input sensitivity figure 5. charge pump output characteristics figure 6. closed-loop phase noise, rf = 12.5 ghz, pfd = 2.5 mhz, loop bandwidth = 20 khz figure 7. ref in sensitivity figure 8. s-parameters ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 0 5 10 15 20 25 rf in lev e l (db) frequency (ghz) 8/9 prescaler 16/17 prescaler 10304-004 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 0 0.5 1.0 1.5 2.0 2.5 3.0 i cp (ma) v cp (v) 0.625ma 1.25ma 1.875ma 2.5ma 3.125ma 3.75ma 4.375ma 5.0ma 0.625ma 1.25ma 1.875ma 2.5ma 3.125ma 3.75ma 4.375ma 5.0ma 10304-005 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100 1k 10k 100k 1m 10m phase noise (dbc/hz) frequency offset (hz) 10304-006 frequency (mhz) 10304-007 ?25 ?20 ?15 ?10 ?5 0 5 10 0 100 200 300 400 500 600 700 800 900 1000 reference sensitivity (dbm) freq mags11 angs11 freq mags11 angs11 freq unit: ghz keyword: r param type: s data format: ma 0.20099200 0.19669930 0.19140480 0.18317790 0.17232760 0.16071930 0.14943970 0.13791310 0.12839340 0.12090700 0.11516160 0.11252430 0.11213720 0.11236920 0.11323590 0.11401910 0.11361600 0.11225360 0.10909150 0.10484100 0.09871251 0.09258573 0.08667851 0.08075383 0.07542522 0.07048169 0.06751262 0.06561201 0.06308079 0.05995205 0.05666475 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8 7.0 7.2 7.4 7.6 7.8 8.0 8.2 8.4 8.6 8.8 9.0 9.2 9.4 9.6 9.8 10.0 ?133.9429000 ?134.7069000 ?135.0024000 ?135.1249000 ?135.0415000 ?135.1840000 ?136.0447000 ?137.7694000 ?140.5623000 ?144.7454000 ?149.8260000 ?155.1801000 ?160.0477000 ?164.5794000 ?168.1217000 ?170.9163000 ?173.2882000 ?175.2539000 ?176.9327000 ?179.0774000 178.5525000 175.9697000 172.5878000 168.3692000 163.5676000 159.0954000 154.6976000 149.2087000 142.2284000 137.8226000 134.1730000 0.05542031 0.05306026 0.05123230 0.04471957 0.03846882 0.03402513 0.04456061 0.05158395 0.06039219 0.05580344 0.08402054 0.10374910 0.11639920 0.13647950 0.16700580 0.18309070 0.19458010 0.20377790 0.21170140 0.21883690 0.22280700 0.22498210 0.22589250 0.22572100 0.22596830 0.23197900 0.24339450 0.26023130 0.28636130 0.31905490 10.2 10.4 10.6 10.8 11.0 11.4 11.8 12.2 12.6 13.0 13.4 13.8 14.2 14.6 15.0 15.2 15.4 15.6 15.8 16.0 16.2 16.4 16.6 16.8 17.0 17.2 17.4 17.6 17.8 18.0 130.0581000 126.9556000 115.8988000 102.0333000 86.3895600 51.1515300 21.0829700 16.8124600 16.5178200 31.4631600 36.3540700 18.8428500 0.2817307 ?15.4473000 ?22.3273100 ?24.3333900 ?25.3870800 ?25.0101800 ?24.2554800 ?23.4312200 ?23.5596400 ?24.411100 ?26.5202700 ?30.3773300 ?36.2808700 ?42.8398200 ?50.7222200 ?57.5844600 ?63.0764200 ?67.5389600 10304-008
ADF41020 data sheet rev. 0 | page 8 of 16 theory of operation reference input section the reference input stage is shown in figure 9. sw1 and sw2 are normally closed switches. sw3 is a normally open switch. when power-down is initiated, sw3 is closed and sw1 and sw2 are opened. this ensures that there is no loading of the ref in pin on power-down. figure 9. reference input stage rf input stage the rf input stage is shown in figure 10. it is followed by a buffer, which generates the differential cml levels needed for the prescaler. figure 10. rf input stage prescaler the ADF41020 uses a two prescaler approach to achieve operation up to 18 ghz. the first prescaler is a fixed divide-by-4 block. the second prescaler, which takes its input from the divide-by-4 output, is implemented as a dual- modulus prescaler (p/p + 1), which allows finer frequency resolution vs. a fixed prescaler. along with the a counter and b counter, this enables the large division ratio, n, to be realized (n = 4(bp + a)). the dual-modulus prescaler, operating at cml levels, takes the clock from the fixed prescaler stage and divides it down to a manageable frequency for the cmos a counter and b counter. the second prescaler is programmable. it can be set in software to 8/9, 16/17, 32/33, or 64/65. it is based on a synchronous 4/5 core. there is a minimum divide ratio possible for contiguous output frequencies. this minimum is given by 4(p 2 ? p). a counter and b counter the a counter and b counter combine with the two prescalers to allow a wide ranging division ratio in the pll feedback counter. the counters are specified to work when the prescaler output is 350 mhz or less. pulse swallow function because of the fixed divide-by-4 block, the generated output frequencies are spaced by four times the reference frequency divided by r. the equation for vco frequency is ?? r f abpf in ref vco ? ???? 4 )( where: f vco is the output frequency of the external voltage controlled oscillator (vco). p is the preset modulus of the dual-modulus prescaler (such as, 8/9, 16/17). b is the preset divide ratio of the binary 13-bit counter (2 to 8191). a is the preset divide ratio of the binary 6-bit swallow counter (0 to 63). f ref in is the external reference frequency oscillator. figure 11. prescalers, a and b counters that make up the n-divide value ref in sw1 sw2 sw3 100k ? nc no nc buffer power-down control to r counter 10304-009 50 ? gnd rf in av dd 3pf buffer to divide by 4 prescaler 10304-010 load load from rf input buffer prescaler p/p + 1 13-bit b counter to pfd 6-bit a counter n divider modulus control n = 4(bp + a) divide by 4 10304-011
data sheet ADF41020 rev. 0 | page 9 of 16 r counter the 14 - bit r counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (pfd). division ratios from 1 to 16,383 are allowed. pfd and charge pump the pfd takes inputs from the r c o unter and n counter and produces an output proportional to the phase and frequency difference between them. figure 13 is a simplified schematic. the pfd includes a fi xed delay element that controls the width of the antibacklash pulse. this pulse ensures that there is no dead zone in the pfd transfer function and minimizes phase noise and reference spurs. the charge pump converts the pfd output to current pulses, whic h are integrated by the pll loop filter. muxout and lock dete ct the output multiplexer on the ADF41020 allows the user to access various internal points on the chip. the state of muxout is controlled by m3, m 2, and m1 in the function latch. figure 17 shows the full truth table. figure 12 shows the muxout section in block diagram form. lock detect muxout can be programmed for two types of lock detect: digital lock detect and analog lock detect. digital lock detect is active high. d igital lock detect is set high when the phase error on five consecutive phase det ector cycles is less than 15 ns . it stays set high until a phase error of greater than 25 ns is detected on any subsequent pd cycle. figure 12 . mux out circuit input shift register the ADF41020 digital section includes a 24 - bit input shift register, a 14 - bit r counter, and a 19 - bit n counter, comprising a 6 - bit a counter and a 13 - bit b counter. data is c locked into the 24 - bit shift register on each rising edge of clk. the data is clocked in msb first. data is transferred from the shift register to one of three latches on the rising edge of le. the destination latch is determined by the state of the two co ntrol bits (c2, c1) in the shift register. c2 and c1 are the two lsbs, db1 and db0, as shown in the timing diagram of f igure 2 . the truth table for these bits is shown i n table 5 . table 5 shows a summary of how the latches are programmed. the spi is both 1.8 v and 3 v compatible. table 5 . c1, c2 truth table control bits data latch c2 c1 0 0 r c ounter 0 1 n c ounter (a and b) 1 0 function l atch ( i ncluding p rescaler) figure 13 . pfd simplified schematic 10304-013 gnd dv dd control mux digital lock detect r counter output n counter output sdout muxout high high d1 d2 q1 q2 clr2 cp u1 u2 up down gnd u3 r divider fixed delay n divider v p charge pump clr1 10304-012
ADF41020 data sheet rev. 0 | page 10 of 16 figure 14 . latch summary figure 15 . reference counter latch map db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 1 0 0 0 1 db21 db22 db23 0 0 1 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) a1 a2 a3 a4 a5 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 a6 db21 db22 db23 g1 0 0 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) f1 pd1 m1 m2 m3 f3 p1 p2 cpi1 cpi2 cpi5 cpi6 tc4 pd2 f2 cpi3 cpi4 db21 tc3 tc2 tc1 db22 db23 f4 f5 reference counter latch reserved 14-bit reference counter control bits reserved 13-bit b counter 6-bit a counter control bits n counter latch cp gain function latch prescaler value power- down 2 current setting 2 current setting 1 timer counter control fast lock mode fast lock enable cp three- state pd polarity muxout control power- down 1 counter reset control bits 10304-014 r14 r13 r12 .......... r3 r2 r1 0 0 0 .......... 0 0 1 1 0 0 0 .......... 0 1 0 2 0 0 0 .......... 0 1 1 3 0 0 0 .......... 1 0 0 4 . . . .......... . . . . . . . .......... . . . . . . . .......... . . . . 1 1 1 .......... 1 0 0 16380 1 1 1 .......... 1 0 1 16381 1 1 1 .......... 1 1 0 16382 1 1 1 .......... 1 1 1 16383 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 1 0 0 0 1 db21 db22 db23 0 0 1 reserved 14-bit reference counter control bits divide ratio 10304-015
data sheet ADF41020 rev. 0 | page 11 of 16 figure 16 . n ( a , b ) counter latch map db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) a1 a2 a3 a4 a5 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 a6 db21 db22 db23 g1 0 0 0 1 1 0 f4 (function latch) fastlock enable 1 1 a6 a5 .......... a2 a1 0 0 .......... 0 0 0 0 0 .......... 0 1 1 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 60 1 1 .......... 0 1 61 1 1 .......... 1 0 62 1 1 .......... 1 1 63 0 0 b13 b12 b11 b3 b2 b1 0 0 0 .......... 0 0 0 0 0 0 .......... 0 0 1 0 0 0 .......... 0 1 0 0 0 0 .......... 0 1 1 3 . . . .......... . . . . . . . .......... . . . . . . . .......... . . . . 1 1 1 .......... 1 0 0 8188 1 1 1 .......... 1 0 1 8189 1 1 1 .......... 1 1 0 8190 1 1 1 .......... 1 1 1 8191 reserved 13-bit b counter 6-bit a counter control bits cp gain a counter divide ratio b counter divide ratio not allowed not allowed 2 operation cp gain charge pump current setting 1 is permanently used. charge pump current setting 2 is permanently used. charge pump current setting 1 is used. charge pump current is switched to setting 2. the time spent in setting 2 is dependent on which fast lock mode is used. see function latch description. n = 4(bp + a), p is a prescaler value set in the function latch. b must be greater than or equal to a. for continuously adjacent values of (n fref), at the output, n min is 4(p 2 ? p). both of these bits must be set to 0 for normal operation. 10304-016
ADF41020 data sheet rev. 0 | page 12 of 16 figure 17 . function latch map 10304-017 p2 p1 0 0 8/9 0 1 16/17 1 0 32/33 1 1 64/65 pd2 pd1 mode 0 0 x 1 0 0 1 0 1 cpi6 cpi5 cpi4 cpi3 cpi2 cpi1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 tc4 tc3 tc2 tc1 0 0 0 0 3 0 0 0 1 7 0 0 1 0 1 1 0 0 1 1 15 0 1 0 0 19 0 1 0 1 23 0 1 1 0 27 0 1 1 1 31 1 0 0 0 35 1 0 0 1 39 1 0 1 0 43 1 0 1 1 47 1 1 0 0 51 1 1 0 1 55 1 1 1 0 59 1 1 1 1 63 f4 0 1 1 m3 m2 m1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 f3 0 1 f2 0 1 f1 0 1 db20 db19 db18 db17 db16 db15 db14 db13 db12 db 1 1 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) f1 pd1 m1 m2 m3 f3 p1 p2 cpi1 cpi2 cpi5 cpi6 tc4 pd2 f2 cpi3 cpi4 db21 tc3 tc2 tc1 db22 db23 f4 f5 f5 x 0 1 neg a tive positive prescaler v alue power- down 2 current setting 2 current setting 1 timer counter contro l f ast lock mode f ast lock enable c p three- s ta te muxout contro l power- down 1 counter reset contro l bits phase detec t or polarit y counter oper a tion norma l r, a, b counters held in reset charge pum p output norma l three-s ta te f ast lock disabled f ast lock mode 1 f ast lock mode 2 f ast lock mode three-s ta te output digi t a l lock detect (active high) n divider output dv dd r divider output rese r ved seria l d at a output dgnd output timeout (pfd cycles) i cp (ma) asynchronous power-down norma l oper a tion soft w are power-down ce pin prescaler v alue pd polarit y 0.625 1.25 1.875 2.5 3.125 3.75 4.375 5.0
data sheet ADF41020 rev. 0 | page 13 of 16 the function latch with c2 and c1 set to 1 and 0, respectively, the on - chip function latch is programmed. figure 17 shows the input data format for programming the function latch. counter reset db2 (f1) is the counter reset bit. when this is 1, the r counter and the n ( a , b ) counter is reset. for normal o peration, this bit should be 0. when powering up, disable the f1 bit (set to 0) . t he n counter then resume s counting in close alignment with the r counter. (the maximum error is one prescaler cycle). power - down bit db3 (pd1) provides a software power - down mode to reduce the overall current drawn by the device. it is enabled by the ce pin. when the ce pin is low, the device is immediately disabled regardless of the state of pd1. in the programmed software power - down, the device powers down immediately after latching 1 into the pd1 bit . pd2 is a reserved bit and should be cleared to 0. when a power - down is activated , the following events occur: ? all active dc current paths in the main synthesizer section are removed. however, t he rf divide - by - 4 prescaler remain s active. ? the r, n, and timeout counters are forced to their load state conditions. ? the charge pump is forced into three - state mode. ? the digital clock detect circuitry is reset. ? the rf in input is debiased. ? the reference input buffer circuitry is disabled. ? the input register remains active and capable of loading and latching data. muxout control the on - chip multiplexer is controlled by m3, m2, and m1 on the ADF41020 . figure 17 shows the truth table. fast lock enable bit bit db9 (f4) of the function latch is the fast lock enable bit. when this bit is 1, fast lock is enabled. fast lock mode bit bit db10 (f5) of the function lat ch is the fast lock mode bit. when fast lock is enabled, this bit determines which fast lock mode is used. if the fast lock mode bit is 0, then fast lock mode 1 is selected ; and if the fast lock mode bit is 1, then fast lock mode 2 is selected. fast lock mode 1 the charge pump current is switched to the contents of current setting 2. the device enters fast lock when 1 is written to the cp gain bit in the n ( a , b ) counter latch. the device exits fast lock when 0 is written to the cp gain bit in th e n (a, b) counter latch. fast lock mode 2 the charge pump current is switched to the contents of current setting 2. the device enters fast lock when 1 is written to the cp gain bit in the n ( a , b ) counter latch. the device exits fast lock under the control of the timer counter. after the timeout period , which is determined by the value in tc4 to tc1, the cp gain bit in the n ( a , b ) counter latch is automatically reset to 0, and the device reverts to normal mode instead of fast lock. see figure 17 for the timeout periods. timer counter control the user has the option of programming two charge pump currents. the intent is that current setting 1 is used when the rf output is stable and the system is in a static state. current setting 2 is used when the system is dynamic and in a state of change (that is, when a new output frequency is programmed). the normal sequence of events follows. the user initially decides what the prefe rred charge pump currents are going to be. for example, the choice may be 0 .8 5 ma as current setting 1 and 1.7 ma as current setting 2. simultaneously, the decision must be made as to how long the secondary current stay s active before reverting to the prim ary current. this is controlled by the timer counter control bits, db14 to db11 (tc4 to tc1), in the function latch. the truth table is given in figure 17 . to program a new output freq uency, simply program the n (a, b) counter latch with new values for a and b. simultaneously, the cp gain bit can be set to 1, which sets the charge pump with the value in cpi6 to cpi4 for a period of time determined by tc4 to tc1. when t his time is up, the charge pump current reverts to the value set by cpi3 to cpi1. at the same time, the cp gain bit in the n ( a , b ) counter latch is reset to 0 and is ready for the next time the user wishes to change the frequency. note that there is an e nable feature on the timer counter. it is enabled when fast lock mode 2 is chosen by setting the fast lock mode bit (db10) in the function latch to 1. charge pump currents cpi3, cpi2, and cpi1 program current setting 1 for the charge pump. cpi6, cpi5, and cpi4 program current setting 2 for the charge pump. the truth table is given in figure 17. prescaler value p2 and p1 in the function latch set the programmable p presc aler value . the p value should be chosen so that the prescaler output frequency is always less than or equal to 350 mhz. pd polarity bit db7 (f2) sets the phase detector polarity bit. see figure 17.
ADF41020 data sheet rev. 0 | page 14 of 16 cp three - state bit db8 (f3) controls the cp output pin. with the bit set high, the cp output is put into three - state. with the bit set low, the cp output is enabled. device programming a fter initial power - up after initial power up of the device, there are three methods for programming the device: function latch, ce pin, and counter reset. function latch method 1. apply v dd . 2. program the function latch load (10 in two lsbs of the control word), making sure that the f1 bit is programmed to a 0. 3. do an r load (00 in two lsbs). 4. do an n ( a , b ) load (01 in two lsbs). ce pin method 1. apply v dd . 2. bring ce low to put the device into power - down. this is an asychronous power - down in that it happens immediately. 3. program the function latch (10). 4. program the r counter latch (00). 5. program the n ( a , b ) counter latch (01). 6. bring ce high to take the device out of power - down. the r and n ( a , b ) counters now resume counting in close alignment. note that after ce goes high, a 1 s du ration may be required for the prescaler band gap voltage and oscillator input buffer bias to reach steady state. ce can be used to power the device up and down to check for channel activity. the input register does not need to be reprogrammed each time t he device is disabled and enabled as long as it is programmed at least once after v dd is initially applied. counter reset method 1. apply v dd . 2. do a function latch load (10 in two lsbs). as part of this, load 1 to the f1 bit. this enables the counter reset. 3. do an r counter l oad (00 in two lsbs). 4. do an n ( a , b ) counter l oad (01 in two lsbs). 5. do a function latch load (10 in two lsbs). as part of this, load 0 to the f1 bit. this disables the counter reset. this sequence provides direct control over the internal counter reset.
data sheet ADF41020 rev. 0 | page 15 of 16 applications information interfacing the ADF41020 has a simple 1.8 v and 3 v spi - compatible serial interface for writing to the device. clk, data, and le control the data transfer. when le goes high, the 24 bits clock ed into the input register on each rising edge of clk are transferred to the appropriate latch. see f igure 2 for the timing diagram and table 5 for the l atch truth table. the maximum a llowable serial clock rate is 20 mhz. aduc7020 interface figure 18 shows the interface between the ADF41020 and the aduc70 19 to aduc7023 family of analog microcontrollers. the aduc70xx family is based on an amr7 core, although the same interface can be used with any 8051 - based micro - controller. the microcontroller is set up for spi master mode with cpha = 0. to initiate the operation, the i/o port driving le is brought low. each latch of the ADF41020 needs a 24 - bit word. this is acc omplished by writing three 8 - bit bytes from the microcontroller to the device. when the third byte is written, bring the le input high to complete the transfer. on first applying power to the ADF41020 , it need s three writes (one each to the function latch, r counter latch, and n counter latch) for the output to become active. i/o port lines on the microcontroller are also used to control power - down (ce input) and to detect lock (muxout configured as lock detect and polled by the port input). when operating in the mode described, the ma ximum spi transfer rate of the aduc7023 is 20 mbps . this means that the maximum rate at which the output frequency can be changed is 833 khz. if using a faster spi clock , en sure a dherence to the spi timing requirements listed in table 1 . figure 18 . aduc70 xx- to- ADF41020 interface blackfin bf527 interface figure 19 shows the interface between the ADF41020 and the blackfin ? adsp - bf527 di gital signal processor (dsp). the ADF41020 needs a 24 - bit serial word for each latch write. the easiest way to accomplish this using the blackfin family is to use the autobuffered transmit mode of operation w ith alternate framing. this provides a means for transmitting an entire block of serial data before an interrupt is generated. set up the word length for 8 bits and use three memory locations for each 24 - bit word. to program each 24 - bit latch, store the th ree 8 - bit bytes, enable the autobuffered mode, and write to the transmit register of the dsp. this last operation initiates the autobuffer transfer. as in the microcontroller case , en sure the clock speeds are within the maximum limits outlined in table 1 . figure 19 . adsp - bf527 - to- ADF41020 interface pcb design guideline s the lands on the l fcsp (cp - 20) are rectangular. the printed circuit board (pcb) pad for these should be 0.1 mm longer than the package land length and 0.05 mm wide r than the package land width. center t he land on the pad to ensure that the solder joint size is maximized. th e bottom of the lfcsp has a central thermal pad. the thermal pad on the pcb sh ould be at least as large as the exposed pad. to avoid shorting, o n the pcb , provide a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad patter n. thermal vias may be used on the pcb thermal pad to improve thermal perf ormance of the package. if vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. the via diameter should be between 0.3 mm and 0.33 mm, and plate the via ba rrel with 1 oz copper to plug the via. connect the pcb thermal pad to gnd. clk data le ce muxout (lock detect) mosi ADF41020 sclock i/o ports aduc70xx 10304-018 clk data le ce muxout (lock detect) mosi ADF41020 sck i/o flags adsp-bf527 gpio 10304-019
ADF41020 data sheet rev. 0 | page 16 of 16 outline dimensions figure 20. 20-lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp-20-6) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADF41020bcpz C40c to +85c 20-lead lead frame chip scale package (lfcsp_wq) cp-20-6 ADF41020bcpz-rl7 C40c to +85c 20-lead lead frame chip scale package (lfcsp_wq) cp-20-6 ev-ADF41020eb1z evaluation board 1 z = rohs compliant part. 0.50 bsc 0.65 0.60 0.55 0.30 0.25 0.18 compliant to jedec standards mo-220-wggd-1. bottom view top view exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indicator 2.30 2.10 sq 2.00 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 1 20 6 10 11 15 16 5 08-16-2010-b ?2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d10304-0-10/12(0)

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